1. Field of the Invention
The present invention relates to solid-state imaging devices, and more particularly, to a solid-state imaging device that achieves a higher pixel density, a higher resolution, less color mixture, and a higher sensitivity.
2. Description of the Related Art
At present, CCDs and CMOS solid-state imaging devices are widely used in video cameras, still cameras, and the like. Performance improvements in solid-state imaging devices, such as an increase in the pixel density, an increase in the resolution, a reduction in color mixture in color imaging, and an increase in the sensitivity, are always demanded. Under such circumstances, in order to realize a higher resolution of solid-state imaging devices, technological innovation such as an increase in the pixel density has been made.
FIGS. 12A to 12B and FIG. 13 illustrate solid-state imaging devices of related art.
FIG. 12A illustrates a cross-section diagram of a solid-state imaging device of an example of related art in which one pixel includes a single island-shaped semiconductor 30 (for example, see Patent Document 1). As illustrated in FIG. 12A, in the island-shaped semiconductor 30 constituting the pixel, a signal line semiconductor N+-region 31 (hereinafter, a “semiconductor N+-region” represents a semiconductor region containing a large amount of donor impurities) is formed on a substrate, which is not illustrated in the drawing. A semiconductor P-region 32 (hereinafter, a “semiconductor P-region” represents a semiconductor region containing acceptor impurities) is formed on the signal line semiconductor N+-region 31. Insulating layers 33a and 33b are formed on the outer periphery of the semiconductor P-region 32, and gate conductive layers 34a and 34b are formed on the outer periphery of the semiconductor P-region 32 with the insulating layers 33a and 33b therebetween. On the outer periphery of the semiconductor P-region 32 above the gate conductive layers 34a and 34b, semiconductor N-regions 35a and 35b (hereinafter, a “semiconductor N-region” represents a semiconductor region containing donor impurities) are formed. On the semiconductor N-regions 35a and 35b and the semiconductor P-region 32, a semiconductor P+-region 36 (hereinafter, a “semiconductor P+-region” represents a semiconductor region containing a large amount of acceptor impurities) is formed in an upper area of the island-shaped semiconductor 30. The semiconductor P+-region 36 is connected to pixel-selecting lines 37a and 37b. The insulating layers 33a and 33b are connected to each other so as to surround the outer periphery of the island-shaped semiconductor 30. Similarly, the gate conductive layers 34a and 34b are connected to each other so as to surround the outer periphery of the island-shaped semiconductor 30, and the semiconductor N-regions 35a and 35b are also connected to each other so as to surround the outer periphery of the island-shaped semiconductor 30.
Regarding the island-shaped semiconductor 30, light, which is one type of electromagnetic energy wave, is applied from the side of the semiconductor P+-region 36 on the upper surface of the island-shaped semiconductor 30. In the island-shaped semiconductor 30, a photodiode region including the semiconductor P-region 32 and the semiconductor N-regions 35a and 35b is formed. Due to this light exposure, signal charges (here, free electrons) are generated in a photoelectric conversion region in the photodiode region. The generated signal charges are stored in the semiconductor N-regions 35a and 35b in the photodiode region. In addition, in the island-shaped semiconductor 30, a junction transistor is formed in which the semiconductor N-regions 35a and 35b serve as a gate, the semiconductor P+-region 36 serves as a source, and a portion of the semiconductor P-region 32 near the signal line semiconductor N+-region 31 serves as a drain. The drain-source current (output signal) of the junction transistor varies in accordance with the amount of signal charges stored in the semiconductor N-regions 35a and 35b and is read to the outside by being extracted outside from the signal line semiconductor N+-region 31. Furthermore, in the island-shaped semiconductor 30, a MOS transistor is formed in which the semiconductor N-regions 35a and 35b of the photodiode region serve as a source, the gate conductive layers 34a and 34b serve as a gate, the signal line semiconductor N+-region 31 serves as a drain, and a portion of the semiconductor P-region 32 between the semiconductor N-regions 35a and 35b and the signal line semiconductor N+-region 31 serves as a channel. When a plus-on voltage is applied to the gate conductive layers 34a and 34b of the MOS transistor, the signal charges stored in the semiconductor N-regions 35a and 35b are discharged to the signal line semiconductor N+-region 31.
The basic operation of the solid-state imaging device includes: a signal charge storing operation for storing into the semiconductor N-regions 35a and 35b signal charges generated in the photoelectric conversion region (photodiode region) by exposure to light beams that are incident from the upper surface of the island-shaped semiconductor 30 in a state where a ground voltage (0 V) is applied to the signal line semiconductor N+-region 31, the gate conductive layers 34a and 34b, and the semiconductor P+-region 36; a signal charge reading operation for reading as a signal current a source-drain current of the junction transistor that is modulated by the potential of the semiconductor N-regions 35a and 35b changed in accordance with the amount of stored signal charges in a state where the ground voltage is applied to the signal line semiconductor N+-region 31 and the gate conductive layers 34a and 34b and a plus voltage is applied to the semiconductor P+-region 36; and a reset operation for, after the signal charge reading operation, discharging the signal charges stored in the semiconductor N-regions 35a and 35b to the signal line semiconductor N+-region 31 in a state where the ground voltage is applied to the semiconductor P+-region 36 and the plus voltage is applied to the gate conductive layers 34a and 34b and the signal line semiconductor N+-region 31.
FIG. 12B illustrates the relationship of the optical absorption intensity I with respect to the Si (silicon) depth (μm) from the light exposure surface of the exposure light wavelength λ for blue light (λ=400 nm), green light (λ=550 nm), red light (λ=700 nm), and infrared light (λ=870 nm). When the optical absorption intensity I is normalized against the optical absorption intensity I0 on the exposure surface, the normalized value I/I0 is reduced against the light penetration depth in an exponential manner. FIG. 12B illustrates that most of blue light is absorbed at a depth of approximately 1 μm; however, green light reaches a depth of 5 μm, red light reaches a depth of 10 μm or more, and signal charges are generated at the depths where the green light and the red light reach. In actual solid-state imaging devices, for example, as described in Non-Patent Document 1, it is required that the depth of a light-sensitive region be set to 2.5 to 3 μm so that 80 percent of green light can be absorbed.
The photoelectric conversion region in the solid-state imaging device illustrated in FIG. 12A is a photodiode region formed by the semiconductor P-region 32 and the semiconductor N-regions 35a and 35b. Thus, due to the reason described above, the height Ld of the photodiode region is required to be 2.5 μm to 3 μm. At present, regarding commercialized solid-state imaging devices, the minimum pitch of two-dimensionally arranged pixels is 1.4 μM. Furthermore, a pitch of 0.9 μM has also been released (see, for example, Non-Patent Document 2). Further reduction in the pixel pitch is demanded. Moreover, since reducing the distance between island-shaped semiconductors 30 constituting pixels adjacent to each other improves the light reception rate which represents how efficiently a light beam is received in the photodiode region and improves the sensitivity of the solid-state imaging device, a reduction in the distance between adjacent island-shaped semiconductors 30 is also demanded. In a case where 0.2 μm (200 nm) is set based on a design rule, normally, processing is performed so that the distance between adjacent island-shaped semiconductors 30 is set as close as possible to 0.2 μm. In this case, the aspect ratio for island-shaped semiconductors (the ratio of the depth to the distance between adjacent island-shaped semiconductors) is 12.5 to 15 or 15 or more. That is, it is required to form the gate conductive layers 34a and 34b of the MOS transistor in a narrow and deep recess formed between island-shaped semiconductors 30. Furthermore, the signal line semiconductor N+-region 31 is required to be formed at the bottom of the island-shaped semiconductor 30. It is therefore difficult to manufacture such solid-state imaging devices. As described above, since the height Ld of the photodiode region is required to be set to 2.5 to 3 μm in the island-shaped semiconductor 30 forming the solid-state imaging device, increases in the pixel density and the sensitivity of the solid-state imaging device are difficult to achieve. Consequently, a technique for reducing the height Ld of the photodiode region without reducing the sensitivity of the solid-state imaging device is demanded.
In addition, at the actual time of imaging, a light beam 38 that is diagonally incident to the island-shaped semiconductor 30, which is a pixel, as illustrated in FIG. 12A, is also incident to the photodiode region of an island-shaped semiconductor 30 adjacent to the island-shaped semiconductor 30 constituting the pixel. Due to a reduction in the light collection ratio in the pixel, signal charges that should be generated in the island-shaped semiconductor 30 constituting one pixel are generated in island-shaped semiconductors 30 constituting peripheral pixels in a distributed manner. Thus, the resolution of the solid-state imaging device is reduced and color mixture in color imaging occurs. Such a problem becomes greater as the pixel density increases.
In addition, a technique exists in which, in order to prevent the light collection ratio from being reduced, metallic walls 39a and 39b are arranged above a photodiode region 41 in a semiconductor device, as illustrated in FIG. 13 (see, for example, Patent Document 2). In this pixel structure, the photodiode region 41 is formed inside a semiconductor substrate 40, and a component isolation region 42 and source and drain regions 43a and 43b of a MOS transistor are formed around the photodiode region 41. Inside a first inter-layer insulating layer 44 formed on the semiconductor substrate 40, a gate electrode 45 of the MOS transistor, a contact hole 46a, and the metallic walls 39a and 39b surrounding the photodiode region 41 are formed. A second inter-layer insulating layer 47 is formed on the first inter-layer insulating layer 44. Furthermore, an SiO2 film 48, an SiN film 49, and a microlens 50 are formed in that order on the second inter-layer insulating layer 47. Contact holes 46b and 46c for circuit wiring are formed inside the second inter-layer insulating layer 47 and metallic wires 51a, 51b, 51c, and 51d are formed on the second inter-layer insulating layer 47.
In the semiconductor device, light beams 52a, 52b, 52c, and 52d transmitted through the microlens 50 are reflected by the metallic walls 39a and 39b and are incident to the photodiode region 41. Thus, the light collection ratio for light beams incident from the microlens 50 to the photodiode region 41 can be improved. However, since the incident light beams are diagonally incident to the surface of the photodiode region 41, part of the light beams 53a, 53b, 53c, and 53d incident to the photodiode region 41 leaks to pixels adjacent to the pixel of interest.
As other techniques for improving the light collection ratio in one pixel, a technique in which a metallic wall is arranged inside a color filter layer formed between a microlens and a photodiode region (see, for example, Patent Document 3), a technique in which a light guide is formed above a photodiode region (see, for example, Patent Document 4), and the like are known. However, even in these techniques, since an incident light beam is diagonally incident to the surface of the photodiode region, part of the light beam incident to the photodiode region leaks to a pixel adjacent to the pixel of interest.